XP4T.SYS · REV 2026.07
FPGA / SoC / ASIC Engineer — Kochi, Kerala
I design and verify digital hardware — from RTL in Verilog and VHDL, through full ASIC back-end flow, to Zynq SoC deployment. Recent work spans CNN inference on FPGA fabric, AXI DMA data-acquisition pipelines, and a complete RTL-to-GDS tapeout in Synopsys ICC2 on 32 nm.
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Project Engineer · Aug 2025 – Present
Delivering FPGA training and faculty development programmes under the MeitY C2S (SMART Lab) initiative. Automating course-management workflows in Python. Published work on deploying PyTorch models to Xilinx FPGAs via Vitis AI.
FPGA Design Intern · Feb – Aug 2025
Designed RTL IP in VHDL for CMV4000-based image acquisition on a Zynq SoC. Built a continuous high-speed capture pipeline across AXI DMA, PS DDR and BRAM, with embedded C control software in Vitis. Validated timing and signal integrity with an MSO.
B.Tech, Electronics & Communication Engineering · Nov 2021 – Apr 2025
Also served as Chairman of the Association for ECE Students (2024–25) and Quality & Operations Lead at the Innovation and Entrepreneurship Development Cell (2024).
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